Architecture of Vedic Multiplier
Essay by iam_tihom • December 10, 2016 • Thesis • 886 Words (4 Pages) • 1,193 Views
CHAPTER 3
ARCHITECTURE OF VEDIC MULTIPLIER
3.1 BASIC ARCHITECTURE
The hardware architecture of 22, 44, 128 bit Vedic multiplier (VM) modules are displayed in the below sections. In 22 bit multiplier, the multiplicand has 2 bits each and the result of multiplication is of 4 bits [5]. So in input the range of inputs goes from (00) to (11) and output lies in the set of (0000, 0001, 0010, 0011, 0100, 0110, 1001). By using Urdhva Tiryakbhyam, the multiplication takes place as illustrated in Figure. 2. Here multiplicands are a0, a1 and b0, b1. The output can be of four digits, say Q3Q2Q1Q0. As per basic method of multiplication, result is obtained after getting partial product and doing addition. The first step in the multiplication is vertical multiplication of LSB of both multiplicands, and then in the second step, that is crosswise multiplication and addition of the partial products. Then Step 3 involves vertical multiplication of MSB of the multiplicands and addition with the carry propagated from Step 2.
Multiplier = a1 a0
Multiplicand = b1 b0
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a1b0 a0b0
a1b1 a0b1
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Q3 Q2 Q1 Q0
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Figure 2: Algorithm for 2×2 multiplier
Product:
Q0: a0b0
Q1: (a1b0) xor (a0b1) (1)
Q2: (a1b1) xor (a1b0 and a0b1) (2)
Q3: (a1b1and a1b0 and a0b1) (3)
[pic 1][pic 2]
Figure 4: Hardware Realization of Generic Adder
The above shown Figure. 4 is an N bit generic adder. Here we are using ripple carry adder where init ially the carry to the first block is zero by default. The carry generated to the first block is applied to the second block and carry generated to second block is applied to the next one and this process is repeated up to the N times. The Boolean function of a generic N bit ripple carry adder can be written as:
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