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Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TETC.2016.2586380, IEEE Transactions on Emerging Topics in Computing



Low-Cost Strategy to Mitigate the Impact of Aging on Latches Robustness

M. Omaña, T. Edara, C. Metra, Fellow, IEEE

Abstract—Analyses recently presented in the literature have shown that the Bias Temperature Instability (BTI) ageing phenomenon may increase significantly the susceptibility to soft errors (SEs) of robust latches. Particularly, this is the case of low-cost robust latches, whose robustness is obtained by increasing the critical charge of their most susceptible node, that is the node most contributing to the latch soft error rate (SER). Therefore, in applications mandating the use of low-cost robust latches, designers will have to face the problem of such latches’ robustness degradation during the IC operation. In order to cope with this problem, we here propose a strategy to reduce the impact of BTI on the SER of standard and low-cost robust latches. It wll be proven that our approach enables to reduce by approximately the 50% the SER increase due to BTI during circuit lifetime with respect to original latches, at limited increase in terms of area overhead, latch setup time and power consumption, and with no impact on the latch input-output delay.

Index Terms— Robust Latch; Soft Error; Aging

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HE continuous scaling of microelectronic technology

SE [9]. Therefore, robust latches in category 2 are less vul-

Tenables to keep on increasing system complexity and

nerable to SEs than latches in category 1. However, they re-

performance. However, this comes together with an in-

quire higher area overhead, power consumption and im-

creased vulnerability to single event transients (SETs) [1,

pact on performance compared to low-cost robust latches

2], possibly compromising the system correct operation. In

in category 1.

particular, SETs affecting latches and flip-flops are becom-

In addition, modern ICs implemented with aggressively

ing a major cause of soft errors (SEs) in sequential circuits

scaled technologies are also becoming increasingly prone

[3, 4, 5, 6], such as modern high performance microproces-

to aging mechanisms, such as bias temperature instability

sors. Consequently, extensive research efforts have been

(BTI) [16, 17]. Negative BTI (NBTI) and Positive BTI (PBTI)

devoted to devise hardening approaches for latches and

are observed in pMOS and nMOS transistors, respectively.


They increase the absolute value of the transistors’ thresh-

Robust latches can be grouped in two categories, de-

old voltage over time, thus resulting in the degradation of

pending on how their increased robustness against SETs is

their driving strenght.

achieved [7]. One category (referred to as category 1) con-

As a consequence, in the last few years, together with

sists of latches that are made robust by increasing the ca-

SET modeling, significant efforts have been devoted also

pacitance  of  some  of  their  nodes  and/or  the  driving

to modeling circuit performance degradation due to BTI

strength of some transistors (e.g., the latches proposed in

(e.g., [18, 19, 20, 21, 22]).  Moreover, it has been recently

[8, 9, 10, 11, 4]). These approaches usually require low area

shown that BTI has also a negative impact on the SE sus-

overhead,  but  do  not  guarantee  complete  immunity

ceptibility of ICs [23, 24, 25]. This because BTI significantly

against SEs. In fact, depending on the hitting particle en-

reduces the value of the critical charge of ICs nodes. In

ergy, SETs may still be generated on internal nodes, possi-

fact, as shown in [26], the critical charge of a node strongly

bly resulting in output SEs. The other category of robust

depends on the value of the restoring current of its pull-

latches (referred to as category 2) consists of latches that are

up/pull-down networks. Since BTI increases the absolute

made robust by proper modification of their internal struc-

value of the transistor threshold voltage over time, it also

ture, making them robust against SEs independently of the

reduces the value of the restoring current of the affected

hitting particle energy (e.g., the latches in [12, 13, 5, 14, 7,

node. As a result, its critical charge reduces, and the likeli-

15]). Consequently, SETs affecting any of the internal or

hood of SET generation increases significantly over time.

output nodes of these robust latches cannot produce an

As previously mentioned, SETs affecting latches and

output SE. Only SETs affecting the input node and satisfy-

flip-flops are the major cause of SEs in sequential circuits.

ing the latch setup and hold times can generate an output

The impact of BTI on the soft error rate (SER) of a standard

latch and robust latches (of both category 1 and category 2)

has been analyzed in [27, 28]. Such analyses showed that


during circuit lifetime, BTI significantly increases the SER

of standard latches and low-cost robust latches in category

M. Omaña and C. Metra are with the University of Bologna (ARCES -

DEI), Bologna 40133, Italy. E-mail: {martin.omana; cecilia.metra}@ un- T. Edara was with the same University.



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