# Large Hadron Collider

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Laboratory Experiment #2 and #3

Combinational Logic Analysis and Design Combinational Logic Circuit Construction and Testing

Prepared by Maneesha Wijesinghe

Performed January 21, 2011 and February 11, 2011

Lab group members:

Rajwinder Murare

Objectives: the objectives of this experiment are to design a combinational logic circuit using the simplified logic expression, simulate the design using PSpice simulation software and construct and test the circuit in the laboratory.

Abstract: Using the Karnaugh map simplification method the expressions for the truth tables given on problem A and problem B were simplified. The simplified expressions, combined with standard logic symbols were used to design a circuit diagram, which implemented the functions using three-input NAND gates. Both functions are simulated via timing diagrams using PSpice simulation software. Using LS7410 (three input NAND gates) the logic circuit designed in problem B was constructed in the laboratory. The circuit was verified by testing various inputs to check if it will give an output accordingly.

Equipment: Tektronix PS 280 DC Power Supply and Tektronix CDM 250 Digital Multimeter.

Theory: The K-map simplification method is used to simplify the logic expressions obtained in this experiment. K-map is a method where the simplification is based on covering the maximum range of values for a given output.

According to the theory in binary code for every time the input value is one the supply voltage should be 5V and every time the input value is 0 the supply voltage should be 0V. The same applies for the output values accordingly.

Procedure: Problem A and B were completed as instructed. Using the breadboard, connectors and LS7410(three-input, NAND gate) the circuit depicted in figure 2 (problem B) was constructed. A 5V power supply was connected to the high terminal and the law terminal was grounded indicating 0V. The pin-out for the 7410 is shown in figure 1.

Figure 1

The circuit was tested by verifying the output for various inputs specified by the instructor. The circuit was verified correct since it provided the expected output according to the truth table.

Data and Analysis:

Problem A:

Truth table:

Decimal A B C F

0 0 0 0 1

1 0 0 1 0

2 0 1 0 0

3 0 1 1 1

4 1 0 0 1

5 1 0 1 1

6 1 1 0 0

7 1 1 1 1

K-map

0

1 3

0 6

0 4

1

1

0 2

1 7

1 5

1

Simplified expression: F = BC +BC + AC

NAND expression: F = BC.BC.AC

Circuit diagram:

Figure2

Timing diagram: attached

Problem B:

Truth table

Decimal A B C G

0 0 0 0 0

1 0 0 1 0

2 0 1 0 0

3 0 1 1 1

4 1 0 0 0

5 1 0 1 1

6 1 1 0 0

7 1 1 1 1

K-map:

0

0 1

0 3

1 2

0

4

0 5

1 7

1 6

0

Simplified Expression: BC + AC

NAND expression: G = AC.BC

Circuit Diagram:

Figure 3

Timing diagram: attached

Conclusion:

The values for the circuit built in lab.

A(V) B(V) C(V) G(V)

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

- When values obtained from the experiment are compared to values from table 2 it can be noticed that they are identical. This implies that the constructed circuit is correct.

- Due to the uncertainty of measurement associated with the equipment the high end voltage and the low end voltage weren't exactly 5V and 0V. Instead, it kept swinging between 5+/- 0.25V and 0+ 0.23V.

End-of-Laboratory report questions

1. What does the term DIP mean?

The term DIP stands for Dual Inline Package, which is an electronic devise package with a rectangular housing and two parallel rows of electrical connecting pins. Basically, DIP contains logic gates.

2. What bias voltage does a standard TTL integrated chip require to operate properly?

5V

3. Describe the integrated chip terminal numbering system.

The pins are numbered counterclockwise

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